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	System Design and Verification Debug Analysis Formal and Static Verification Planning and Management Simulation and Testbench Software-Driven Verification Verification IP Digital Design and Signoff Equivalence Checking Low-Power Validation Synthesis Power Analysis SDC and CDC Validation Silicon Signoff Test Custom IC / Analog / RF Design Library Characterization Circuit Design Circuit Simulation Electrically Aware Design Layout Design Layout Verification RF Design Variation-Aware Design Modeling IC Package Design and Analysis IC Package Design SI/PI Analysis Integrated Solution SI/PI Analysis Point Tools Cross-Platform Co-Design and Analysis PCB Design and Analysis Design Authoring PCB Layout Library and Design Data Management Analog/Mixed-Signal Simulation SI/PI Analysis Integrated Solution SI/PI Analysis Point Tools Others PCB manufacturing tooling and analysis Failure Analysis
	IP solutions

Digital Design and Signoff > Silicon Signoff

	Pegasus Verification System	Cadence Design Systems, Inc.

	Quantus QRC Extraction Solution	Cadence Design Systems, Inc.

	Tempus Timing Signoff Solution	Cadence Design Systems, Inc.

	Assura Physical Verification	Cadence Design Systems, Inc.

	Physical Verification System	Cadence Design Systems, Inc.

	CMP Predictor	Cadence Design Systems, Inc.

	MaskCompose Reticle and Wafer Synthesis Suite	Cadence Design Systems, Inc.

	QuickView Signoff Data Analysis Environment	Cadence Design Systems, Inc.

	LDE Electrical Analyzer	Cadence Design Systems, Inc.

	Process Proximity Compensation	Cadence Design Systems, Inc.

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