Predict and reduce systematic and parametric variations due to
chip topography and layer thickness


Key Benefits 

  •  Accurately predicts multi-layer thickness and topography variability for the entire
     layer stack using a model-based approach developed with model calibration tool,
     Cadence CMP Process Optimizer

  •  Detect hotspots that affect yield and produces fixing guidelines during implementation
     through integration with Cadence Virtuoso Layout Suite and Cadence Innovus
     Implementation System at chip or block level

  •  Interfaces with Cadence Quantus QRC Extraction Solution to identify timing-related
     problems and potentially reduce process guardbands

  •  Enables CMP teams to detect CMP hotspots on incoming designs, optimize the CMP
     manufacturing parameters, and improve overall systematic and parametric variations
  

Cadence® CMP Predictor predicts the Chemical and Mechanical Polishing (CMP) variations and their
potential impact on your design for the entire layer stack. It turns the uncertainty of manufacturing
process variation into predictable impacts, and then minimizes these impacts during the design stage
to greatly enhance overall design performance and yield, at the chip level and also at IP level with CCP
unique block-based methodology. CMP predictor allows silicon calibration of semi-physical models and
optimization of CMP material and process parameters. CMP Predictor provides full-chip, multi-level
thickness and topography predictions for the entire stack, covering FEOL, MEOL, BEOL, dielectric
deposition, copper electrochemical deposition (ECD), etch depth, and copper/dielectric planarization
processes.

CMP-related hotspots, such as copper pooling, can have detrimental effects on chip yield. The
conventional rules-based approach to hotspot detection fails to capture long-range and multi-level
CMP effects. CMP Predictor uses a highly accurate model-based approach to finding potential hotspot
areas. It also feeds the thickness and topography variation data into extraction tools, enabling better
RC and timing analysis.

Cadence CMP Predictor integrates with Cadence Virtuoso® Layout Suite, Cadence Innovus™
Implementation System and  interfaces closely with the Cadence Quantus™ QRC Extraction Solution
for a complete silicon signoff solution.