Accelerates time to design closure


Key Benefits 

  •  Advanced timing signoff solution with comprehensive analysis  

  •  Integrated with Cadence Innovus Implementation System 

  •  Integrated with Cadence Virtuoso platform 
  

Cadence® Tempus™ Timing Signoff Solution is a complete standalone tool that delivers silicon-accurate
timing signoff and signal integrity analysis that ensures operational chips after tapeout. By tightly
coupling the design implementation environment with the timing signoff environment, the Tempus
solution enhances timing convergence throughout the design flow and greatly reduces the time to
design closure.

As well as being a stand alone tool, Tempus Timing Signoff Solution integrates with both Cadence Innovus™
Implimentation System and the Virtuoso® Platform. 

  •  Integrated with Cadence Virtuoso platform

       •  Automatic abstraction of digital components and timing paths
       •  Automatic parasitic extraction
       •  Common Open Access database for seamless integration
       •  Cross-probing of timing paths from timing report to Virtuoso Layout Suite layout editor

  •  All-in-one mixed-signal package for small embedded digital logic which includes:

       •  SDC lint checks
       •  SDC policy checks, including hierarchical checks
       •  SDC integration