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Designers need a good high-level language to do high-level synthesis, and C++delivers that. Since SystemC is C++, SystemC users get all those benefits. Since we're doing hardware, we have to be able to specify bit-widths. SystemC is the IEEE standard for this. Some C++ synthesis vendors try to lock you in with a proprietary class library. And there are the items like hierarchy, concurrent simulation, and the ability to write your own interfaces that are required for designs with a lot of control as well as datapath elements. These are also required for a verification flow that doesn't force you down.
SystemC has all of the necessary constructs to support a wide spectrum of electronic design requirements from ESL and system design down to block-level, extending all the way from system software to RTL. Design teams can describe system-level and block-level detail with the same language. They can express embedded software and embedded hardware in the same language. This allows the hardware/software partition decisions to be made later in the design process.
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• Cynw_p2p interface classes
• Memory generator
• Buffer interface
• Circular buffer interface
• Line buffer interface
• Trigger-done interface
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CellMath Designer（CMD）is an innovative datapath synthesis tool that automatically creates high quality gate-level designs optimized for power, area, and timing. CMD easily integrates into your existing Cadence, Synopsys, or Magma IC design flow by utilizing industry standard tool interfaces and data formats. CMD reads standard Verilog RTL models extended with datapath pragmas and automatically produces an optimized Verilog gate-level netlist. CMD also produces bit-accurate C and hierarchical Verilog models to support your simulation and formal verification process respectively. Your target technology is installed via standard cell libraries in the Synopsys Liberty forma（.lib）. CMD reads your design constraints using the Synopsys Design Constraints（.sdc）format. |
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Cynthesizer Ultra uses CellMath Designer as an embedded datapath optimization capability to create datapath components as needed for use in the high-level synthesis process. These products work together to perform automated design-space exploration that will search for the best set of components for each individual design. With these techniques, Cynthesizer Ultra improves power consumption and timing, and reduces area by up to 40% compared to previous versions.
Cynthesizer Ultra adds access to the CellMath IP library including advanced, floating point functional units used by leading-edge graphics companies. This IP can be accessed directly from SystemC through an automated flow. |
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