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The first H.264-E core was introduced in 2006. The current core is based on a second generation design
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The core support Baseline Profile, up to level 5.1 |
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The core can be targeted to any ASIC or FPGA devices
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It’s video quality and ease of integration
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No. The standard allows for a great freedom on algorithms selection and implementation. For example, video quality strongly depends on Motion Estimation, and algorithms for mode-selection and rate-control.
In our case, we use the most powerful motion estimation algorithm（i.e. full-search）and the full coding tools that the standard provisions for motion estimation（i.e. Variable Block Size Motion Estimation, and ¼ pet accuracy）. As far as mode-selection and rate control we use proprietary, innovative algorithms, that provide very high quality along all kinds of video contents and resolutions. |
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We cannot provide comparison data of our core versus competitive cores. However, we encourage and help our customers to perform their own comparisons. To this end we provide a bit-accurate software model, reference designs, and support. |
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The flexible streaming capable interfaces, the fact the RTL is scan insertion and time closure friendly, the stand-alone operation, the efficient memory interface, the run-time encoding parameters programmability, and the respect to decoders buffering requirements. |
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Avalon-Streaming is the native interface, but wrappers for AHB and AXI4 can also be made available.
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The fact that a host processor would only need to program the core’s configuration registers. From that point forward the core assumes no external processing on the incoming stream. It receives the YUV data, can handle scan conversion, and output in NAL byte stream format.
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Because it requires a relatively low-bandwidth from the external memory and it is tolerant to latencies. Furthermore, it is independent from memory type, so a user can select its memory of preference（DDR3, DDR2, SDRAM, QSRAM etc）.
The interface is based on access requests, and therefore connecting to most memory controllers is straightforward. Finally the core can be made pin-compatible to Xilinx, Altera and CAST memory controller cores.
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