Advanced statistical exploration of your design


Key Benefits 

   •   Easily enables the appropriate analysis by letting you simply choose
       your task (e.g., yield verification) or statistical corner creation and
       specify your target sigma requirement

   •   Provides high-yield estimation capabilities for checking the outer
       boundaries of your design at the 4-, 5-, or 6-sigma level

   •   Delivers advanced statistical sample reordering that greatly improves
       the performance of the statistical simulation, with additional speed-up
       for FinFET technology at 16nm and below

   •   Provides mismatch contribution analysis and statistical sensitivity
       analysis to pinpoint most influential devices within a statistical simulation

   •   Features easy, one-step creation of worst-case corners as derived by
       3-sigma statistical sampling
  

The Cadence® Virtuoso® ADE Variation Option extends the statistical variation
capabilities of Cadence’s Virtuoso ADE Assembler and Virtuoso ADE Verifier to allow for
more sophisticated statistical analyses to be performed on any design. Specialized
technology is also available for advanced-node designs.


Statistical sample reordering 

Directly addresses the significant challenges associated with 3-sigma design, especially
at an advanced process node or low Vdd. Virtuoso ADE Variation Option provides a
statistical approach to verify circuit yield or create corners efficiently by reordering the
samples to simulate the worst samples first. The method is co-developed with major
foundries to provide with additional speedup for FinFET technology at 16nm and below.


High-yield estimation for 4-, 5-, or 6-sigma analysis

Parametric high-yield estimation is often required on devices that have extremely high
volume (i.e., memory devices), or when testing the circuit limits is a must when failure
of the part is not an option (i.e., automotive safety or medical devices). The Virtuoso
ADE Variation Option provides two methods of simulation to meet and match your needs
and conditions:

   •   Scaled-sigma sampling (SSS): This preferred statistical method generates
        samples where the standard deviation has been scaled up which is more accurate
        than WCD for nonlinear behavior and more efficient when there is a large number of
        statistical parameters and specifications.

   •   Worst-case distance (WCD): This statistical method defines the shortest distance
        from the nominal point to the specification boundary in the process/mismatch
        parameter space. WCD typically requires under 100 simulations for each spec and so
        is suitable for designs with a small number of specs/parameters that need to be
        monitored/changed.


Automated yield improvement flow

Virtuoso ADE Variation Option has an “Improve Yield” command that will return a design to
a state where it meets all of the design criteria and has the highest possible yield. If no such
point has been reached it will run iterative analyses on the current criteria and determine
the conditions for highest possible yield for that design.


Mismatch contribution analysis

Virtuoso ADE Variation Option has a mismatch contribution analysis feature which is a Monte
Carlo post-processing feature that helps in identifying the important contributors to mismatch
variation. You can then modify the identified devices in the schematic and make the design
less sensitive to mismatch variation