Faster and higher quality verification at block, chip, and system levels

Key Benefits
 
  •  Eliminates misrepresentations that lead to bug escapes

  •  Provides rapid environment construction, scalability, and reuse

  •  Automates test generation with up to 5X faster runtime
  

Incisive® Specman® Elite automates testbench generation and reuse, providing multi-language
support and an advanced debug option. The tool supports industry-standard verification languages
and is compatible with the Open Verification Methodology (OVM), the Universal Verification Methodology
(UVM), and the eReuse Methodology (eRM), so you can quickly and easily integrate it with established
verification flows. It also provides an environment for working with, compiling, and debugging testbench
environments written in the e language.

Incisive Specman Elite uses executable specifications and designer-specified constraints to automate
testbench generation, while simultaneously detecting misrepresentations of the specification. Its
automated data and assertion checking speeds debug, while its functional coverage analysis capability
drives verification using the metric-driven verification methodology. With automated testbench
generation, you can boost verification productivity at block, chip, and system levels. 

The Incisive Specman Elite hardware verification language is supported on industry-standard simulators.
As with other languages and standards, the Incisive Enterprise Simulator native compiler for IEEE
1647 e language provides superior runtime performance, multi-language support including Accellera
UVM-ML OA, and advanced debug capabilities.
  

Specman Advanced Option

Available as an add-on to Incisive Enterprise Specman simulator, the Specman Advanced Option combines
dynamic loading and reseeding techniques (both available in e) to greatly boost verification and debug
productivity. You can run a simulation up to a certain point, save its state, and resume it in multiple
processes later on. You can restore simulation states and reseed them to increase coverage, and also
dynamically load new files after restoring to guide future results.

Bypassing lengthy start-up functionality, the Specman Advanced Option allows you to quickly locate the
most meaningful portion of your simulations; achieve higher functional coverage; reduce test development
and debug cycles; reduce regression runs; and save hundreds of simulation hours.


Key Features
 
  •  Captures executable specifications to eliminate misrepresentations that lead to bug escapes
 
  •  Leverages the e language’s unique aspect-oriented programming (AOP) capabilities for rapid
      environment construction, scalability, and reuse

  •  The “IntelliGen” AOP constraint solver automates test generation with up to 5X faster runtime,
      unprecedented distribution control, and scalability for more than 1 billion logic gate devices

  •  Automates data and assertion checking for faster debug

  •  Tracks industry-standard coverage metrics (functional, transactional, HDL) for higher verification
      quality

  •  Supports a proven metric-driven verification solution that applies UVM-MS for digital-centric mixed-
      signal verification to achieve first-pass success

  •  Creates reusable sequences and multi-channel virtual sequences on top of an e verification
      environment

  •  Comprehensive language support includes e, Open Verification Library (OVL), OVM class library, UVM
      class library, SystemC, SystemVerilog, Verilog, VHDL, PSL, SVA, C/C++ models, MATLAB models, and
      analog models in Verilog-A, VHDL-A, wreal, and SPICE

  •  Works with all major simulators, with a high-speed direct kernel interface when used inside Incisive
      Enterprise Simulator