Accelerates IC power signoff and overall design closure


Key Benefits 

   •   Transistor-level power grid and signal net EMIR accuracy, performance, and accuracy
       by Cadence Spectre simulator and its patented, voltage-based, iterated matrix-solving
       technology

   •   Foundry enablement and certification on EM rules and IR-drop accuracy on advanced
       FinFET and FD-SOI nodes

   •   Seamless integration in Cadence Virtuoso Digital Implementation platform for highly
       efficient analog/mixed-signal EMIR analysis, debug, and fixing

   •   Comprehensive, single path in the Virtuoso flow from Cadence Physical Verification
       System/Assura DRC/LVS to Quantus QRC Extraction Solution to Virtuoso ADE/Spectre
       EMIR, Voltus-Fi Custom Power Integrity Solution, and Virtuoso Layout Suite

   •   Power-grid view macro model generation for top-level, full-chip Voltus tool power
       signoff
  

Cadence® VoltusTM-Fi Custom Power Integrity Solution is a transistor-level electromigration and
IR-drop (EMIR) tool that delivers foundry-certified SPICE-level accuracy in power signoff. 

EMIR presents unique challenges at the transistor level, from complex EM rules to the high costs of
simulating for current on a large RC network at post-layout. Enabled via an integration with our
Spectre® Accelerated Parallel Simulator signoff SPICE simulation solution, Voltus-Fi Custom Power
Integrity Solution shortens power signoff closure and analysis through:

   •   Our patented voltage-based iteration method, which calls for a smaller memory footprint and
        runs faster than the industry's traditional current-based iteration method. In the first stage,
        a RC reduced simulation is run to collect the voltage profile at tap device points. Then, the
        collected profile is applied to the entire RC network to simulate all sub-node states for
        voltage/current and to generate EMIR reports.

   •   Integration with our Virtuoso® platform, providing a single design flow for better productivity
        in the analog and custom block EMIR signoff process

   •   Integration with Voltus IC Power Integrity Solution, resulting in a seamless flow for advanced
        analog/mixed-signal power signoff for designs that have mixed transistor-level and cell-level
        blocks


Fastest Design Closure Flow

The combined use of Voltus-Fi Custom Power Integrity Solution and Voltus IC Power Integrity Solution,
tightly integrated with several other Cadence tools, provides the industry's fastest design closure flow.

   •   Get a unified electrical signoff flow with Cadence Tempus™ Timing Signoff Solution and our
        Quantus™ QRC Extraction Solution
   •   Bring power grid design to the early stage of physical implementation with an early rail analysis
        capability via the Cadence Innovus™ Implementation System
   •   Get accurate IC power integrity analysis, driven by real-world power simulation vectors, with
        Cadence Palladium® technology
   •   Benefit from chip-package-PCB co-simulation and analysis with Cadence Allegro® Sigrity®
        technology