Delivers 2.5D and 3D full-chip parasitic extraction and analysis
 

Key Benefits 

   •   Best-in-class accuracy using smart solvers; trusted by customers
        with multiple tapeouts validated in working silicon

   •   Massively parallel architecture delivers fastest extraction runtimes
        with linear scalability to 100s of CPUs

   •   Fully certified down to 7nm process at TSMC and all other leading
        foundries 

   •   Comprehensive, accurate, and trusted EMIR solution with Cadence
        Voltus-Fi Custom Power Integrity Solution for all FinFET designs 

   •   Built-in 3D field solver, Quantus FS, is foundry certified and used for
        critical nets and other designs 


The Cadence® Quantus™ QRC Extraction Solution is the industry's most trusted
signoff parasitic extraction tool. As a single, unified tool, the Quantus solution
supports both cell-level and transistor-level extractions during design implementation
and signoff. It’s an integral component of our in-design methodology with both the
Innovus™ Implementation System and Virtuoso® platforms. Furthermore, with its
tight integration with the Tempus™ Timing Signoff Solution, it provides the fastest
timing signoff turnaround times. 

The Quantus solution is built on massively parallel technology and includes an
integrated, foundry-certified 3D field solver, Quantus FS. The Quantus solution
provides linear scalability to 100s of CPUs in addition to providing the fastest runtimes
for single- and multi-corner extraction. It delivers silicon-proven accuracy with 1000s
of tapeouts for all process nodes across all foundries 

Our customers have trusted the Quantus solution and Quantus FS for all types of
designs such as system-on-chip (SoC), custom-digital, image sensors, power MOSFETs,
standard-cell, IP, SRAM/bitcell, DRAM and other memories, and custom-analog designs. 

The Quantus solution provides significant differentiated silicon-proven functionality for
all designs. Some of these features include: 

   •   Up to 5X reduction in turnaround time using Integrated Virtual Metal Fill (IVMF)
        versus real Metal Fill GDS 
   •   Accurate inductance extraction for both GDS and LEF/DEF with accuracy of less
        than 10% versus FastHenry, an industry standard for golden inductance extraction
        tool 
   •   Up to 6X reduction in simulation runtimes using advanced parasitic reduction
        functionality 
   •   Accurate substrate noise analysis (SNA) functionality with less than 5% accuracy
        with silicon measurement 
   •   Less than 5% accuracy versus silicon measurements for automotive devices
        extraction such as PowerMos 
   •   And many more…