Complete IC packaging design and analysis solution for advanced
fan-out wafer-level chip-scale package 


Key Benefits

   •   Production- and foundry-proven flow with multiple tapeouts

   •   Direct integration with PDK-driven PVS DRC/verification provides graphical
        designer feedback minimizing path to tapeout readiness

   •   Advanced WLP-specific metal creation and management removes/reduces
        eco spins

   •   High-performance GDSII processing shortens path to tapeout readiness

NOTE: Cadence Physical Verification System (PVS) is mandatory for the WLP design flow
but must be purchased separately.
  

The Cadence® SiP Layout Advanced WLP Option in conjunction with the Cadence Physical
Verification System (PVS) delivers flexible advanced wafer-level package (WLP) design
coupled with process development kit/rules deck (PDK)-driven design rule checking
(DRC), verification, and mask signoff suitable for emerging silicon wafer-based packaging
methodologies, and has been validated by TSMC for their Integrated Fan-Out (InFO) process. 


The Cadence SiP Layout Advanced WLP Option in conjunction with PVS enables designers to
address the common advanced (WLP) design and fabrication challenges of:

   •   Adherence to a PDK from the WLP manufacturer for DRC, verification, and mask signoff

   •   PDK-required fan-out wafer-level package (FOWLP)-specific interconnect (metal) density
        creation and management to control fabrication warpage

   •   High-performance GDSII mark processing

   •   2D and 3D extraction, model, and analysis for signal and power integrity performance
        and stability (through optional Cadence Sigrity™ technology)