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Efficient definition and constraint management
Key Benefits
• Schematic designers and layout engineers can work in parallel
• Advanced productivity features, such as reuse of previous schematic
designs as blocks or sheets
• Smooth integration into pre-layout simulation and signal analysis
• TÜV SÜD “Fit for Purpose – TCL1” certified to meet ISO 26262 automotive
functional safety requirements
Cadence® Allegro® Design Authoring is
an enterprise-enabled design creation
solution that allows schematic designers
to create complex designs quickly and
efficiently. It provides advanced productivity
features such as reuse of previous schematic
designs as blocks or sheets—partially or
completely.
Oriented around team-based development,
Allegro Design Authoring allows schematic
designers and layout engineers to work in
parallel. Users can capture physical and
electrical constraints and assign design rules
with the embedded Allegro Constraint
Manager. |
Allegro Design Authoring allows
schematic designers and layout
engineers to work
in parallel.
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Integrated with Allegro AMS Simulator for analog and digital simulation and SI
analysis, Allegro Design Authoring also offers multiple options for FPGA integration.
Automotive TCL1 Certified for ISO 26262
The industry’s first PCB design and verification flow to achieve “Fit for Purpose -
Tool Confidence Level 1 (TCL1)” certification enables you to meet stringent ISO
26262 automotive safety requirements. The flow includes everything from design
authoring to simulation to physical realization and verification using the PSpice®,
Allegro, and OrCAD® product suites. The high-performance design entry, simulation,
and layout editing tools provide an integrated environment for design engineers to
validate the safety specifications against individual circuit specifications for design
confidence. For information on the safety manuals, Tool Confidence Analysis (TCA)
documents, and compliance reports from TÜV SÜD, download the Functional Safety
Documentation Kits through Cadence Online Support.
Features
• Provides schematic and
HDL/Verilog design input
• Assigns and manages
high-speed design rules
• Supports net classes,
buses, extended nets, and
differential pairs
• Eliminates rework with
powerful library creation
and management
• Allows synchronization of
logical and physical design
• Enables multi-user parallel
development with systematic
version control
• Integrates smoothly into
pre-layout simulation and signal
analysis
• Supports customizable user interface
and enterprise deployment |
Users can capture physical and electrical
constraints and assign design rules with the
embedded Allegro Constraint Manager.
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