The I/O layer of a chip is a critical and time-sensitive aspect of a chip development. While the I/O specification can be a moving target in a chip development lifecycle, it is imperative the I/O implementation be fully synchronised across design & verification teams, and between front & back-end teams. As bugs in the I/O layer are typically blocking in design flows and critical in silicon, the need to be eliminated entirely from chip development

SPINNER is an award-winning out-of-the-box solution that solves these challenges.

SPINNER manages the complete specification of an I/O layer of a complex chip and enables a fully-automated, correct-by-construction creation of the I/O layer, including documentation, RTL design and verification infrastructures
 
The effects of increasing chip complexity have produced many challenges for efficient I/O integration, sometimes putting it on the critical path of a chip development. Spinner is the only out-of-the-box solution that specifically focuses on and addresses this challenges.
 
Through high-levels of automation and perfect-by-construction methodologies, Spinner has proven a 20x reduction in costs related to complex SoC I/O integration. Spinner has an immediate turnaround time and its high-quality output facilitates rapid system-level verification hook-up and has been proven to deliver a 20% reduction in the overall chip integration schedule.

Spinner offers an extensive feature set distributed across design/verification, front-end/back-end teams and includes innovative I/O library management and standardised interfaces. It also includes the ability to tailor all generated outputs to match your design flow
 
The rationale for using Spinner as the single source solution for complete I/O layer automation is undisputable when customers begin to leverage the full power of the tool.