Reduces test time without impact on design size or fault coverage


Key Benefits

   •   Up to 3X reduction in test time without impact on design size or fault
        coverage

   •   Up to 2.6X reduction in compression logic wirelength

   •   Natively integrated with the Genus™ Synthesis Solution

   •   RTL insertion of Programmable MBIST

   •   Programmable MBIST: Support for ARM MBIST Interface

  
Concerned about your test costs? Reduce your SoC test time by up to 3X with the
Cadence® Modus™ Test Solution. Introducing a new patented 2D Elastic Compression
architecture, this next-generation tool enables compression ratios beyond 400X
without impacting design size or routing. With a complete suite of industry-standard
capabilities for memory BIST, logic BIST, testpoint insertion, and diagnostics, the solution
can help you reduce your production test costs and increase silicon profit margins. 


Key Features

The 2D Elastic Compression architecture in the Modus Test Solution consists of:

   •   Modus 2D Compression: XOR compression logic forms a physically aware 2D grid
        across the chip floorplan, enabling higher compression ratios with reduced wirelength.
        At 100X compression ratios, wirelength for 2D compression can be up to 2.6X smaller
        than current industry scan compression architectures.

   •   Modus Elastic Compression: Registers embedded in the decompression logic enable
        fault coverage to be maintained at compression ratios beyond 400X by controlling
        care bits sequentially across multiple scan cycles during ATPG.

   •   Integration with Synthesis and Implementation Flows: All Modus DFT logic insertion
        is natively integrated within the Genus Synthesis Solution cockpit. The solution’s
        Modus ATPG component also shares a common Tcl scripting and debug language with
        the Genus Synthesis Solution, the Innovus™ Implementation System, and the Tempus™
        Timing Signoff Solution, streamlining flow development and simplifying user training
        across a complete Cadence digital flow.

   •   Embedded Memory Bus Support: Integrate seamlessly with macro interface for at-speed
        PMBIST across multiple embedded memories in an IP core and support for ARM MBIST
        interface. New programmable test algorithms for FinFET SRAMs and automotive safety
        applications are also included with this feature.