Providing formal verification technology for fast,
accurate bug detection and correction


Key Benefits 

  •  Exhaustively verifies multi-million–gate ASICs and FPGAs several times faster than
      traditional gate-level simulation 

  •  Decreases the risk of missing critical bugs with independent verification technology 

  •  Enables faster, more accurate bug detection and correction throughout the entire design flow 

  •  Extends equivalence checking capability to complex datapaths and closes the RTL-to-layout
      verification gap (XL configuration) 

  •  Ensures RTL models perform the same functions as the corresponding transistor circuits
      implemented on silicon (GXL configuration) 
  

Cadence® Conformal® Equivalence Checker (EC) makes it possible to verify and debug multi-million–gate
designs without using test vectors. It offers the industry’s only complete equivalence checking solution for
verifying SoC designs—from RTL to final LVS netlist (SPICE)—as well as FPGA designs. Cadence Conformal
EC enables designers to verify the widest variety of circuits, including complex arithmetic logic, datapaths,
memories, and custom logic.

Already proven in thousands of tapeouts, Conformal EC is the industry’s most widely supported independent
equivalence checking product. It is production-proven on more physical design closure products, advanced
synthesis software, ASIC libraries, and IP cores than any other formal verification technology.