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  Vendor: Cadence Design Systems, Inc.  
  Product Name: Virtuoso Liberate AMS Mixed-Signal Characterization Solution  
  Product Introduce:    

 

Offers 20X faster characterization of post-layout netlists


Key Benefits 

   •   Unparalleled operational efficiency and user flexibility with highly
       scalable systems


   •   Advanced compiler, predictable runtime, and debug capabilities

   •   Offers 20X faster characterization of post-layout netlists
  

Cadence® Virtuoso® Liberate™ AMS mixed-signal characterization solution enables
fast and accurate characterization of large mixed-signal macros to create instance-
specific memory models for timing, power, and noise.

The Liberate AMS solution extends Cadence’s ultra-fast standard cell and I/O library
characterization capabilities to cover large mixed-signal macro blocks such as phase-
locked loops (PLLs), data converters (ADCs, DACs), SerDes, high-speed transceivers,
and high-speed I/Os. Macro blocks require additional pre-analysis steps in order to
make fast and accurate characterization feasible. Leveraging a network of distributed
CPUs and utilizing the “hybrid partitioning” technology for optimizing characterization
runtime, mixed-signal macros can be characterized quickly and easily with the same
accuracy and methods as standard cells, including the generation of timing constraints
and modeling of current source models for timing, power, and noise.

   •   Read article on “Library "Safe Margins"—Are They Really Saving Your Design?”


Features

   •   Automates the creation of standard Liberty models for large mixed-signal macro
        blocks by automatically capturing the interaction between digital and analog paths
        to identify latches, flops, and other probe nodes

   •   Improved throughput comes from “hybrid partitioning” technology, comprised of
        a full-block view and partitioned sub-block views to characterize large macro blocks
        efficiently and accurately

   •   Full-block view is used to characterize power and drive the creation of sub-block
        partitions

   •   Integrated with Virtuoso Analog Design Environment, enabling the reuse of test-
        benches and existing setup to quickly move from circuit design validation into library
        generation




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