Accurately measure RTL power consumption during design exploration


Key Benefits 

  •  RTL within 15% of signoff power

  •  Up to 20X faster time-based power analysis

  •  Bridge between verification, implementation and signoff

  •  Direct integration with Palladium platform for quick peak power identification
  

Getting an accurate measure of RTL power consumption during design exploration has long been a
major challenge for SoC design teams. System-level verification tools have the capacity to exercise real
use cases, but they are disconnected from the implementation tools that translate RTL to gates and
wires and from signoff tools that validate the final design.

Cadence® Joules™ RTL Power Solution closes this gap by delivering time-based RTL power analysis with
system-level runtimes and capacity while still providing high-quality estimates of gates and wires.

Built on a multi-threaded frame-based architecture, the Joules RTL Power Solution delivers 20X faster
time-based RTL power analysis as compared to other methods. The tool also incorporates rapid prototype
technology from Cadence Genus™ Synthesis Solution that can analyze designs of up to 20 million
instances overnight with gate-level accuracy of within 15 percent of signoff. In addition, the Joules
RTL power solution integrates seamlessly with Cadence Palladium® Accelerator/Emulator for early
system-level power analysis and optimization.