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The core can optionally support upto 30 quality layers for greyscale images, LCRP progression, PLT and TLM markers. Therefore it can compress greyscale images according to the NPJE, TPJE and SPJE BIIF profiles.
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We provide Bit-Accurate Software Model（BAM）, which can be used to assess video quality with your own clips. Furthermore, we provide a reference design, based on PCIe for raw and compressed video exchange, that can enable rapid integration to your application.
The reference design is available in source RTL, or as a targeted FPGA netlist, or mapped in commercially available FPGA prototyping boards.
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See Table：
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Yes. The core is silicon proven since 2004.
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Yes. The core can be targeted to any ASIC or FPGA devices
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Yes, we provide a technology independent soft-PHY
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Yes, we provide an OS-independent low level driver written in C.
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Wide support for devices and standards, ease of integration, and low host-processor overhead.
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Because it is provided in technology independent RTL or FPGA netlists, it supports multiple bus architectures（OCP, AHB, OPB/PLB, Avalon, FlexBus, etc.）, it embeds high performance DMA controllers, it is run time adaptable to connected devices, it enables straightforward timing closure and scan-insertion, and it allows trading features for area during synthesis.
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Because, the core implements in custom hardware processing steps like Bad Block Management, AES256 encryption, ECC etc that in some other cases are handled in software. Furthermore the core is capable of handling transfers, spanning in multiple pages, relieving the host from page management.
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