INTRODUCTION
This document describes the direct digital clock synthesis technology developed by Motorola Labs Transceiver Research known as the Multiple Reference Clock Generator（MRCG）. The technology is available to customers as IP distributed through IPextreme, Inc. The MRCG IP integrated with a DLL and a single PLL provides a low power, very flexible implementation of a clock synthesizer capable of generating multiple clocks in an SoC design.
The MRCG technology was developed as a flexible clock reference signal for integrated digital processing applications with a direct digital synthesis feature set. Some additional objectives were：
‧ Overcome the limited flexibility of PLL clocks such as frequency change locked loop transit
‧ Limited 20% voltage controlled oscillator（VCO）tuning range
‧ Generation of phase offset and other coherent signal pairs
Some of the MRCG signal source features are：
‧ Cycle-to-cycle frequency, time, or phase shifting
‧ 1 GHz to 2 MHz operating frequency range with one VCO reference
‧ Reconfigurable complex signal function generation
‧ Generation of multiple independent coherent signal set
