Silicon IP, or SIP, has become essential to the semiconductor supply chain and is the cornerstone for most complex nanometer SoC designs. Over the past 15 years, SIP has shortened development cycles, reduced development cost and risk, enabled complex SoC design, and allowed design groups to focus on product differentiation rather than wheel reinvention.
While these are all benefits of high-quality SIP, designers have also learned that using poor SIP can have nasty consequences. Many pioneering IP users have stories of late development projects, unexpected and expensive silicon respins, and worse results from choosing bad SIP. It’s true that most providers of bad IP have now disappeared through natural selection in the marketplace, but it is unfortunately still possible to end up with a poor choice of SIP for your particular project. So yes, SIP quality is still very much an issue for most designs.
Efforts to objectively measure SIP quality go back to the early stages of SIP evolution. Attempts to set standards and metrics for the quality of SIP deliverables and verification—or at least to define best practices—include the Reuse Methodology Manual, VSIA’s QIP spreadsheet, and innumerable panel discussions and internal IP team debates.
