Abstract
Low K1 photolithography process increases the complexity of RET applications in IC designs. As technology node shrinks, pattern density is much denser along with much smaller geometry dimensions. Model-based OPC（Optical Proximity Correction）and post-OPC verification require more complex models and through process window compensated approaches, which significantly increase computational burden. Both lithographical challenges and computational complexity associated with 45nm process and below create a need for advanced capabilities on commercial OPC tools. To answer those challenges, hardware-accelerated OPC solution made a debut to solve runtime bottleneck issues, but they came in with very expensive price tags. As today, there are no explorations on the linkage between design styles and layout pattern OPC reusability.
This paper introduces a new OPC flow with pattern-centric approach to leverage OPC knowledge of repeated design cells and patterns to achieve fast full chip OPC convergence, shorter cycle time, better OPC quality, and eventually lead to high manufacturing yields. In this paper, the main concepts of pattern-based OPC flow are demonstrated in 65nm customer memory designs. Pattern-based OPC is a natural extension of Anchor's pattern-centric approaches in DFM（Design for Manufacturing）domain.
Keywords：Pattern-based OPC, pattern-centric approach
