Engineers enter false paths on a design for a variety of reasons. A path may be specified false because it is between two asynchronous clock domains, or because the path originates from a static register whose value never changes, or because the path is a timing don’t care. In this paper we focus on paths that are specified false because the engineer believes the path is impossible to sensitize. Engineers specify such paths as false because they believe the combination of logic values required to sensitize the path is not possible based on the functionality of their design.
Static sensitization is an approach to false-path verification that establishes if the required combination of values is possible to sensitize a path. If the combination is impossible a falsepath definition is considered good. If it is possible then the false-path definition is considered bad. However, it is important to consider not just the functionality of the chip but circuit delay when determining if a path is sensitizable.
Dynamic sensitization refers to the fact that while in any given clock cycle, the static state of a design may be such that a path cannot be sensitized, the dynamic nature of the design（once timing delays are accounted for）may temporarily allow the design to enter the state necessary to sensitize a path. Dynamic sensitization allows glitches to propagate through paths that are statically false. It is important that false-path definitions established using static sensitization are safe under dynamic sensitization, i.e. that static sensitization does not incorrectly mask real timing problems by underestimating the true delay on a design.
