Features
★ Highly flexible and customizable DFI 3.1 compliant DDR controller architecture
★ Supports up to 32 target interfaces including AXI, AHB and FIFO-based interfaces
★ User-customizable arbiter (scheduler)


Uniquify’s DFI 3.1 compatible DDR Controller provides a simple and flexible interface for accessing external DDR SDRAM memory. It provides advanced power saving features such as automatic entry into active power down, precharge power down, and self refresh. It achieves high performance through maximum utilization of multiple open banks and command look ahead.

The DDR Controller can optionally operate at the same clock frequency as the SDRAM memory (full-rate mode) or at half the clock frequency of the SDRAM memory (half-rate mode).

The Controller comes configured with one or more “targets” based on the design requirements needs — from 1 to 32 or larger as required. Supported targets include AXI, AHB and a custom FIFO-based target. Each one supports many customizations such as data path width, transfer length, read and write data buffering and byte enable support. Verilog testbench tasks and C routines that perform controller initialization and SDRAM initialization are provided to simplify integration of the IP and bring-up.

The Controller includes a very flexible arbiter that shares access to the Controller across all of the targets. Many different schemes can be implemented including minimum number of consecutive accesses, minimum bandwidth, bandwidth optimization, prioritization based on request, and many others.