Uniquify is a provider of leading edge SoC design and IP solutions. Our IP portfolio includes
our patented DDR subsystem IP featuring our SCL (self-calibrating logic) and DSCL (dynamic
SCL). SCL and DSCL improve system reliability and yield by automatically compensating for
both static and dynamic variations in the DDR timing interface. The portfolio also includes many
other IP blocks commonly utilized in today's leading edge SoC designs.

Our design experts have extensive experience in meeting stringent power, clocking, IP integration,
and performance requirements for today's most challenging ASIC and SoC designs.