High-Performance, Configurable, 8051-Compatible, 8-bit Microcontroller Core

This 8051 IP core implements a range of fast, 8-bit, 8051-compatible microcontrollers that execute the MCS®51 instruction set.

The R8051XC2 IP core runs with a single clock per machine cycle, and requires an average of 2.12 machine cycles per instruction. Dhrystone 2.1 tests show it to run from 9.4 to 12.1 times faster than the original 8051 at the same frequency. Representative 90 nm ASIC results have reached 430 MHz, for an effective speed-up of 400 times over 80C51 chips.

The configurable core has a rich set of optional features and peripherals. Designers can choose from several versions, including the easy-to-configure full version with all options included; a custom, non-configurable version with options specified at purchase; and pre-packaged versions with different sets of options and degrees of configurability.

All versions of this 8051 core benefit from power-saving architectural efficiency—the R8051XC2 is 10% better in milliwats/DMIP than our previous generation—and various power-management options are available. System development is facilitated through a native on-chip debugging option and support by development tools from Keil and IAR.

This product builds on CAST’s experience with hundreds of 8051 IP customers going back to 1997. Designed for easy reuse in ASICs, structured ASICs, or FPGAs, the core is strictly synchronous, with positive-edge clocking (except in the optional debug & SPI modules), synchronous reset, and no internal tri-states. Representative 90nm ASIC results show the core to be conservative in its use of space, requiring just 8,000 to 71,000 gates.


Applications

The 8051 continues to be a rigorous and cost-effective solution for many applications, and the fast, flexible R8051XC2 is an especially good choice for many systems. Popular uses include data management control for complex systems, and interface control for analog and sensing chips.


Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available; contact CAST Sales.


Verification

The core has been verified through extensive simulation and rigorous code coverage measurements. All subcomponents were functionally verified with an HDL testbench using their individual test suites. The CPU and ALU have been verified against a proprietary hardware modeler and behavioral models. The peripherals have also been verified in their own testbenches, based on either hardware or behavioral models. An extensive constrained random verification was performed to verify the CPU, DMA and OCDS.


Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

      •   HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
      •   Easy-to-use configuration tool (with configurable versions)
      •   An example chip implementation, which uses the core in a sample system
      •   Sophisticated self-checking HDL Testbench including everything needed to test the core (Verilog versions 
          use Verilog 2001)
      •   Simulation script, vectors, and expected results
      •   Synthesis script (ASICs) or place and route script (FPGAs)
      •   Comprehensive user documentation, including detailed specifications and a system integration guide

A reference design board is available; contact CAST Sales for information.


Available Versions

Three versions of this 8051 core are available, offering a range of capabilities and prices. (See block diagrams below.)

R8051XC2-F includes the full set of options, and is user-configurable (i.e., options may be included or excluded prior to synthesis).

R8051XC2-A includes options that match the original Intel 8051 peripheral set: 64kB memory interface, two timers, one serial port, four parallel I/O Ports, two-level interrupt controller, and two DPTR registers. These options are user-configurable (i.e., may be deleted prior to synthesis).

R8051XC2-B includes options that match the Infineon 80515/80517 peripheral set: 64kB memory interface, three timers, two serial ports, four parallel I/O ports, watchdog timer, multiplication-division unit, and two DPTR registers. These options are user-configurable (i.e., may be deleted prior to synthesis).

ASIC (RTL) and FPGA (netlist) deliverables are available; FPGA packages are not user-configurable.