The Block Memory Generator LogiCORE™ IP core automates the creation of resource and power optimized block memories for Xilinx® FPGAs. Available through the (add ref to Vivado™) ISE® Design Suite CORE Generator™ System, the core enables users to create block memory functions to suit a variety of requirements. Built-in knowledge about Xilinx device architectures allow it to leverage specialized FPGA architectural features to create the most compact, high performance or low power solution.

A Migration Kit is available to automate the migration to latest version of the core.

Key features are:
 •  Choice of Native Interface, AXI, or AXI4-Lite
 •  Example Design helps you get up and running quickly
 •  Native interface core
       •  Generates Single-Port RAM, Simple Dual-Port RAM, True Dual-Port RAM, Single-Port ROM, or Dual-Port ROM
       •  Performance up to 450 MHz
       •  Data widths from 1 to 4096 bits
       •  Memory depths from 2 to 128k
       •  Variable Read-to-Write aspect ratios in Virtex®-7, Kintex®-7, Virtex-6, Virtex-5 and Virtex-4 FPGAs
       •  Option to optimize for resource or power
       •  Ability to initialize the memories with pre-defined values
       •  Supports individual write enable per byte in Virtex-7, Kintex-7, Virtex-6, Virtex-5, Virtex-4, Spartan®-6 and Spartan- 3A / XA DSP with or without parity
       •  Selectable per-port operating mode: WRITE_FIRST, READ_FIRST or NO_CHANGE
       •  Support for hard and soft Error Correction (ECC) feature
 •  AXI interface core
       •  Generates Dual Port RAM
       •  Performance up to 300 MHz
       •  Data widths ranging from 8 to 64 bits
 •  Common features in Native interface and AXI cores
       •  Variable port aspect rations for dual-port configurations
       •  VHDL and Verilog behavioral models optimized for fast simulation times
       •  Structural simulation model option for precise simulation


Documentation
The COTS version v7.3 is the baseline from which the DO-254 Block Memory Generator 1.00a comes from. Logicircuit applies the DO-254 lifecycle to this COTS version. As a result of this DO-254 process, the source code will be modified with the goal of achieving 100% code coverage, and the resulting code will be named DO-254 Block Memory Generator 1.00a. Below are links to the Xilinx® Product Data for the version that was used as the basis, and the Logicircuit Data Sheet of the resulting DO-254 product.

Link to the Xilinx® Product Guide
 
Link to the Logicircuit Data Sheet: DO-254 Block Memory Generator 1.00a Data Sheet


Device Family Support
Xilinx® Artix™-7
Xilinx® Kintex™-7
Xilinx® Virtex™-7
Xilinx® Zynq™-7000
Xilinx® Spartan®-6