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Important Features
‧ Decode all MP3 bit streams under 9 MHz Clock,
‧ 45 K gates in logic plus 13K bytes on chip data memory, no program ROM needed,
‧ Ten-band equalizer with 64 steps for -20 to 20 dB gain,
‧ Thirty-two steps volume control,
‧ Superior music quality,
‧ Straightforward user interface,
‧ Hand-crafted optimized data path with complete hard-wired logic,
‧ Fully synthesizable technology independent of verilog RTL code
Interface
Why MP3-SO3E is the best choice for MP3 decoding chip？
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Technology
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MP3-SO3E
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ARM7
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Clock rate required
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9 MHz
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25 Mhz
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Logic gate*
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45K |
75K
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Program ROM *
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None
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30K bytes
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Data RAM*
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13K bytes
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30K bytes
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Total gate count:
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45+13*8=104 K gates
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75+30*8+8=323 K gates
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Volume control
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Yes
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Yes
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10 band equalization
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Yes
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No
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Integration time
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-4 weeks by one experienced ASIC engineer |
10-15 weeks for a couple of experts in the field of RISC/DSP processor integration.
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Software Issue
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None
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10-15 weeks to develop the API
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| Cost |
Relative low
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10-15 weeks to develop the API
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*Assuming, 4 ROM cell = 1 gate count, 1 RAM cell = 1 gate count, ARM7 core logic =45k gates, the interface logic for ARM7 30～50k gates.
In general, DSP cores consume similar silicon area as ARM7 does.
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