The ARINC 818 transceiver core provides an easy way to implement ARINC 818 compliant interfaces in Xilinx® FPGAs. The core can achieve ARINC 818 interfaces up to 4.25. GRT offers evaluation kits and development packages that greatly simplify implementing ARINC 818. The core can be used for transmit only, receive only, or for transmit and receive applications. The core has many flexible compile time settings allowing for various link speeds, line segmentations, and line synchronization methods. The core can be configured for various resolutions and pixel packing methods. Ancillary data can use default values set at compile time or data can be updated in real time via register interface.

Key features are:
 •  Complete header/ancillary data recovery
 •  Embedded ancillary data with real time update
 •  Flexible video resolution/frame rates
 •  Low Latency
 •  Many pixel packing and input formats
 •  Progressive and interlaced video
 •  Receiver error and status detection
 •  Simple pixel bus transmitter interface
 •  Supports V5, V6 and S6
 •  Supports line synchronous transmission
 •  Supports link speeds up to 4.25 Gbps


Documentation
The COTS version v2.0 is the baseline from which the DO-254 ARINC 818 XGA Transceiver Core 1.00a comes from. Logicircuit applies the DO-254 lifecycle to this COTS version. As a result of this DO-254 process, the source code will be modified with the goal of achieving 100% code coverage, and the resulting code will be named DO-254 ARINC 818 XGA Transceiver Core 1.00a. Below are links to the Xilinx® Product Data for the version that was used as the basis, and the Logicircuit Data Sheet of the resulting DO-254 product.
 
Link to the Great River Technology
 
Link to the Logicircuit Data Sheet: DO-254 ARINC 818 XGA Transceiver Core 1.00a Data Sheet


Device Family Support
Xilinx® Spartan®-6