The new Display SerDes is designed specifically for next generation flat panel displays, integrating a low power macro with a fine resolution, low jitter video clock to drive new video standards such as V-by-One HS®. The New Analog Bits Display SerDes 　o　 Reduce Power 　o　Reduced Footprint 　o　Reduce Costs 　o　Customized to You Needs From the Integrated Clocking & Interface IP Leader

Features：
　‧　 Programmable analog front end supports V-by-One HS standard
　‧　Configured as an 8-lane octal transmit macro that fits in 0.44 sq.mm
　‧　 Industry leading low power – typically 4.5mW/Gbps/lane running at 3.75Gbps
　‧　Test and configuration support for ac-JTAG, power-down modes, PLL bypass modes
　‧　Low pin-count and suitable for a variety of wire-bond packages
　‧　Customized configuration widths, metallization scheme and pad structures
　‧　Integrates with an external V-by-One logical control layer to form a complete transmit
　‧　Physical Layer（PHY）