Processor Core

The  MD5 encryption IP core is a fully compliant hardware implementation of the Message Digest Algorithm MD5, suitable for a variety of applications. It computes a 120-bit message digest for messages of up to (264– 1) bits.

The MD5 algorithm is an improved version of the MD4, created by Professor Ronald L. Rivest of MIT, and is closely modeled after that algorithm. It operates on message blocks of 512 bits for which a 128-bit (4 x 32-bit words) digest is produced. Corresponding 32-bit words of the digest from consecutive message blocks are added to each other to form the message of the whole message.

The MD5 core is a fully synchronous design and has been evaluated in a variety of technologies. It is available optimized for ASICs or FPGAs.


Applications

The high-performance MD5 core is suitable for a variety of applications, including:

      •   Electronic funds transfer 
      •   Authenticated electronic data transfers 
      •   Encrypted data storage


Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.


Verification

The core has been verified through extensive synthesis, place and route and simulation runs. It has also been embedded in several products, and is proven in FPGA technologies.


Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

      •   HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
      •   Sophisticated HDL Testbench (self checking)
      •   C Model & test vector generator
      •   Simulation script, vectors & expected results
      •   Synthesis script
      •   User documentation