| |
Programmable Advanced Encryption Standard Core
The AES-P encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths.
Two architectural versions are available to suit system requirements. The Standard version (AES32-P) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES128-P) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. It can be programmed to use any of the following cypher modes: ECB, CBC, OFB, CFB and CTR.
The core works with a pre-expanded key, or with optional key expansion logic.
The AES-P core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.
Applications
The AES-P can be utilized for a variety of encryption applications including:
• Protected network routers
• Electronic financial transactions
• Secure wireless communications
• Secure video surveillance systems
• Encrypted data storage
Support
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Verification
The core has been verified through extensive synthesis, place and route and simulation runs. It has also been embedded in several products, and is proven in FPGA technologies.
Deliverables
The core is available in ASIC (RTLL) and FPGA (netlist) forms, and includes everything required for successful implementation:
• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Sophisticated HDL Testbench (self checking)
• C Model & test vector generator
• Simulation script, vectors & expected results
• Synthesis script
• User documentation
|
