The WMA-SO2 decoder ASIC core is designed for low power WMA decoding applications.
The WMA-SO2 can be seamlessly integrated with Silicon Ocean MP3 decoder MP3-SO3E for a new generation of low power, low cost MP3/WMA decoding chips.

1.   Important Features
　‧　All WMA decoding functions implemented at RTL level
　‧　Gate count 75 K gates plus 22K bytes data RAM
　‧　Lowest power consumption（clock required 9 MHz）
　‧　Single clock synchronous design
　‧　Support WMA audio decoding
　‧　Straightforward interfaces for SoC applications
　‧　Ten-bands equalizer with 64 steps for -20 to 20 dB gain
　‧　Thirty-two steps volume control
　‧　Fully synthesizable technology independent of verilog RTL code

2. Function Overview
　WMA-SO2 takes any WMA bitstream, automatically detects the header and extracts all header/side information,
　and then uses the information to decode compressed WMA bit stream. The output from the WMA-SO2 is 16 bits
　PCM samples. These PCM samples can be transferred to audio DAC via I2S bus or through a rate converter to
　a low cost fixed sample rate audio DAC.

3. WMA-SO2 top level interface


　　


Deliverables
　‧　Synthesizable verilog source code
　‧　Verilog testbench