Munich, Germany – August 10th, 2021 – Codasip, the leading supplier of customizable RISC-V®
embedded processor IP, announced today that Mythic, the pioneering AI processor company with
breakthrough analog compute-in-memory technology, has selected Codasip's L30 (originally Bk3)
RISC‑V‑based core for Mythic's next generation Analog Matrix Processor (Mythic AMP™). 


Mythic uses Codasip RISC-V cores in its revolutionary new M1076 Mythic AMP™, which delivers
best-in-class performance, scalability, and power efficiency. Mythic's Analog Matrix Processor is
designed with an array of tiles, and each contains: a large Analog Compute Engine (ACE) to store
neural network weights and perform matrix multiplications; local SRAM memory for data being
passed between the neural network nodes; a single-instruction multiple-data (SIMD) unit for
processing operations not handled by the ACE; and a Codasip processor for controlling the
sequencing and operation of the tile. Using Codasip Studio, Mythic customized Codasip's processor
IP to meet the unique computing requirements of the M1076 AMP.  


“Codasip's RISC-V cores and customization toolset helped us accelerate the design of our new
M1076 AMP while giving us the flexibility we needed to offer an unparalleled combination of
performance and power efficiency,” said Ty Garibay, Vice President of Engineering at Mythic.
“We look forward to continuing our engagement with Codasip on the next generation of our
groundbreaking processors for cutting-edge AI applications.”


“We have been thrilled to see the launch of Mythic's revolutionary Analog Matrix Processor,” said
Dr. Karel Masařík, CEO and Founder of Codasip, “We are very excited to have been chosen for the
company's next artificial intelligence processor design.”


The Codasip L30 processor is based on the RISC-V open instruction set architecture (ISA). It is
optimized for low power and area efficiency. It has a single 3-stage processor pipeline architecture,
optional caches, optional Floating Point Unit, Multiplication and Division, JTAG and RISC-V debug,
and industry standard bus interfaces (AMBA). It also includes support for privilege-mode and
memory protection via standard RISC-V PMP, making it an attractive alternative to legacy,
proprietary microcontroller cores. L30 is fully configurable and extensible in compliance with the
RISC-V standard. 


About Codasip

Codasip delivers leading-edge RISC-V processor IP and high-level processor design tools, providing
IC designers with all the advantages of the RISC-V open ISA, along with the unique ability to
customize the processor IP. As a founding member of the RISC-V Foundation and a long-term
supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for
embedded processors. Formed in 2014 and headquartered in Munich, Germany, Codasip currently
has offices in Europe and China, with sales representatives worldwide.
For more information about our products and services, visit www.codasip.com.
To learn more about RISC-V, visit www.riscv.org.