PLDA's CXL Verification IP Ecosystem is intended to reduce the
challenges of designing new CXL applications. By combining
leading third-party VIP and PLDA's best-in-class CXL controller IP,
CXL designers will have the ability to choose the most flexible and
complete solution for their SoC designs, eliminating reliance on
single-source suppliers – an essential step to reducing design risk. 


PLDA's CXL Verification IP Ecosystem addresses this challenge by
enabling several pre-integrated testbenches designed by Avery
Design System and Truechip with their respective VIPs and
testsuites. The verification ecosystem provides in-depth
verification of a complete solution with feature-aligned IP and VIPs
for CXL 2.0 and the PCIe 5.0 specifications. Pre-integrated
testbenches are already available to customers. They can by now
initiate their evaluation, and greatly speed-up the early verification
stages of their IP integration. 

		XpressLINK Controller:       •     Supports the CXL 2.0              specification       •     Implements the CXL.io,              CXL.mem, and              CXL.cache protocols       •     Supports all 3 defined              CXL device types       •     Supports Host, Device,              Switch ports and Dual              Mode/shared silicon              implementation

		XpressLINK-SOC Controller IP for CXL supports:       •     The AMBA AXI Protocol              Specification for CXL.io              traffic       •     Either the Intel              CXL-cache/mem Protocol              Interface (CPI), the AMBA              CXS-B Interface or the              AMBA AXI Protocol              Specification for              CXL.mem       •     Either a CPI interface or the              AMBA CXS-B Protocol              Specification for CXL.cache              traffic.

 




Please feel free to contact us if you have any questions or have
an active project that you would like to discuss.


Best regards,

PLDA Team 




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