PLDA and Alphawave, a leading provider of multi-standard connectivity
IP solutions for electronic devices, today announced a collaboration
designed to provide the industry's most robust IP solutions for
interconnect technologies most commonly used today such as PCIe®
5.0 and CXL™. They will also begin collaborating on future technologies
including PCIe 6.0. 


The partnership delivers an integrated Controller and PHY solution, using
PLDA's leading IP controllers for PCIe and CXL and Alphawave's
high-performance, low-power DSP PHY IP. This combined solution gives
high-end SoC and ASIC designers a tightly-integrated solution that
reduces latency and power while ensuring highest data transfer efficiency.
These features are especially important in bandwidth-intensive designs
such as those used in datacenter, artificial intelligence, and automotive
applications.  


The PLDA and Alphawave collaboration provides an end-to-end solution
for PCIe and CXL that is latency optimized and specially tailored to
applications leveraging CXL.mem and CXL.cache protocols. Key
features of the combined solution include:

          •   A silicon-proven PCIe 5.0 SerDes PHY IP from Alphawave for
              both original PIPE and SerDes architecture modes that easily
              satisfies the latency requirements for memory-centric
              applications.

          •   A silicon-proven IP controller from PLDA for CXL and PCIe that
              is architecturally-optimized for low-latency and that supports a
              large number of added features designed to dramatically
              improve performance and simplify integration. 


                                          

For more information on the PLDA and Alphawave products, contact PLDA
or visit the companies’ websites:

          •   PLDA CXL Controller 

          •   PLDA PCIe Controller
 
          •   Alphawave PHY 








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