XpressPCS for PCIe 5.0 is a logic design IP core implementing
the Physical Coding Sublayer part of the PCIe 5.0 Specification.
XpressPCS is the ideal solution for PHY IP vendors and
technology companies developing their own SerDes PHY
looking to complement their SerDes PMA implementations with
a full-featured silicon proven PIPE-compliant interface.


XpressPCS exposes:

       •   A PIPE compliant user interface allowing connection to
            any PIPE 5.2 and PIPE 4.4.1 compliant PCIe PHY/MAC.
       •   A transmit and receive interface to the PHY/PMA
            electrical sub-block along with messaging interface for
            Equalization and Lane Margining functionality.

                                  XpressPCS Controller IP  


The comprehensive PHY/PMA interface is the result of years
working with PCIe SerDes developers and guarantees
XpressPCS IP can be used with any SerDes PMA implementation. 

Please feel free to contact us if you have an active project that
you would like to discuss or if you have any other questions.

We will be happy to schedule a call with our FAEs to address
any questions that you may have and collaborate with you in
the future!     






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