We are launching a series of webinars on our BrightTALK channel. Don't miss our 1st event : "Breaking the PCIe Latency Barrier with CXL"As the Compute Express Link™ (CXL™) interconnect protocol is gaining in popularity, mainly driven by the promise of higher performance and lower latency for CPU to Device communication, many questions arise around expected latency improvement. In this presentation, we describe the data flow model for the 3 protocols that comprise CXL (CXL.io, CXL.cache, CXL.mem) in contrast to traditional PCI Express, and look at the implications in terms of latency at the system level. We then present a couple of specific use cases that would clearly benefit a lower latency CXL interconnect and conclude with a look at the PLDA Controller IP for CXL and the design features allowing optimal CXL performance in silicon chips.
Save your seat
|
XpressLINK IP for CXL 2.0
• Implementation of the CXL.io, CXL.mem, and CXL.cache protocols
• Support for all 3 defined CXL device types
• Support for the PCI Express 5.0 Base Specification, Revision 1.0
• Support for the PIPE 5.x specification with 8-, 16-, 32-, 64-, and 128-bit configurable PIPE interface width |
Please feel free to contact us if you have an active project that you would like to discuss or have any other questions.
We will be happy to schedule a call with our FAEs to address any questions that you may have and collaborate with you in the future!
Copyright© 2020 PLDA, All rights reserved.
|