PLDA Technical Expert speaks at PCI-SIG DevCon Fall on a hot topic:
Prototyping and Hardware Validation of PCIe 5.0 designs at 32 GT/s
The number of silicon chips supporting PCIe 5.0 is already ramping
up at leading edge foundries, while PCIe 4.0 has only begun to hit
the market with the first commercial platforms. Nonetheless, the
data rate promised by PCIe 5.0 technology is reaching its physical
limit at 32GT/s speed, introducing a slew of constraints at various
levels: PCB track topology restrictions, PCS requirements, etc. In
this presentation we list and explain the challenges facing PCIe 5.0
hardware validation and prototyping, and propose ways to address
these challenges.
Watch now
Don't miss the Q/A session at 6:00 PM on Tuesday, October 27th
Add to your schedule
Watch how we demonstrate PCIe® 5.0 Link Training at 32 GT/s
between PLDA's PCIe 5.0 controller and Broadcom PHY
The demo showcases stable PCIe 5.0 Link Training (32 GT/s)
and exceptional signal integrity with a Broadcom® PCIe 5.0
PHY platform.
Discover PLDA PCIe 5.0 Solutions
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XpressRICH-AXI
Controller IP for PCIe® 5.0
Supporting Root Port, Endpoint,
Dual-mode Configurations, with
Optional Built-in DMA and
Configurable AMBA® AXI
Interconnect
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XpressRICH
Controller IP for PCIe 5.0
Supporting Root Port,
Endpoint, Dual-mode, Switch
Port Configurations, with
Native User Interface
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XpressPCSPHY/PCS
Physical Coding Sublayer
Logical Sub-Block IP Core for
PCIe supporting PCIe 5.0, 4.0,
3.1 PHY/PMA and compliant to
the PIPE 5.2 and 4.4.1
Specifications |
XpressSWITCH
PCIe 5.0 Multi-port Transparent
Switch IP Core with 1 Upstream
Port and up to 31 Downstream
Ports
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Please feel free to contact us if you have an active project that you
would like to discuss or have any other questions.
We will be happy to schedule a call with our FAEs to address any
questions that you may have and collaborate with you in the future!
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