Rambus Delivers PCIe 6.0 Interface Subsystem for High-Performance
Data Center and AI SoCs


Highlights:

     •    Delivers data rate of up to 64 GT/s for high-performance workloads
     •    Supports the full feature set of PCIe 6.0 with PHY support for CXL 3.0
     •    Offers complete IP solution optimized for latency, power, and area
     •    Provides cutting-edge security to protect valuable data assets


SAN JOSE, Calif. — (BUSINESS WIRE) — October 24, 2022 — Rambus Inc. (NASDAQ: RMBS),
a premier chip and silicon IP provider making data faster and safer, today announced the availability
of its PCI Express® (PCIe®) 6.0 Interface Subsystem comprised of PHY and controller IP. The
Rambus PCIe Express 6.0 PHY also supports the latest version of the Compute Express Link™
(CXL™) specification, version 3.0.


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https://www.businesswire.com/news/home/20221024005307/en/




PCIe 6.0 Interface Subsystem (Graphic: Rambus Inc.)


“The rapid advancement of AI/ML and data-intensive workloads is driving the continued evolution
of data center architectures requiring ever higher levels of performance,” said Scott Houghton,
general manager of Interface IP at Rambus. “The Rambus PCIe 6.0 Interface Subsystem supports
the performance requirements of next-generation data centers with premier latency, power, area
and security.”


The Rambus PCIe 6.0 Interface Subsystem delivers data rates of up to 64 Gigatransfers per second
(GT/s) and has been fully optimized to meet the needs of advanced heterogenous computing
architectures. Within the subsystem, the PCIe controller features an Integrity and Data Encryption
(IDE) engine dedicated to protecting the PCIe links and the valuable data transferred over them.
On the PHY side, full support for CXL 3.0 is available to enable chip-level solutions for cache-coherent
memory sharing, expansion and pooling.


“PCIe is ubiquitous in the data center and CXL will become increasingly important as companies
pursue ever-escalating speeds and bandwidths to support higher levels of performance in
next-generation applications,” said Shane Rau, research vice president, Computing Semiconductors
at IDC. “As a growing number of chip companies emerge to support new data center architectures,
access to high-performance interface IP solutions will be key to enabling the ecosystem.”


Key features of the Rambus PCIe 6.0 Interface Subsystem include:

     •    Supports PCIe 6.0 specification including 64 GT/s data rate and PAM4 signaling
     •    Implements low-latency Forward Error Correction (FEC) for link robustness
     •    Supports fixed-sized FLITs that enable high-bandwidth efficiency
     •    Backward compatible to PCIe 5.0, 4.0 and 3.0/3.1
     •    State-of-the-art security with an IDE engine (controller)
     •    Supports CXL 3.0 for new use models that optimize memory resources (PHY)


More Information:
For more information on the PCIe 6.0 Interface Subsystem,
please visit rambus.com/interface-ip/serdes/pcie6-phy/.


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Twitter: @rambusinc
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About Rambus Inc.
Rambus is a provider of industry-leading chips and silicon IP making data faster and safer. With
over 30 years of advanced semiconductor experience, we are a pioneer in high-performance
memory subsystems that solve the bottleneck between memory and processing for data-intensive
systems. Whether in the cloud, at the edge or in your hand, real-time and immersive applications
depend on data throughput and integrity. Rambus products and innovations deliver the increased
bandwidth, capacity and security required to meet the world’s data needs and drive ever-greater
end-user experiences. For more information, visit rambus.com.