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Optimize implementations for performance and cost
Key Benefits
• Automates selection and placement of decoupling capacitors
• Ensures power-delivery system needs are met, at lowest decap costs
• Recaptures usable design area used by unnecessary decaps
To ensure you get high performance at a system and component level, while at the
same time saving between 15% and 50% in decoupling capacitor (decap) costs,
Cadence® Sigrity™ OptimizePI™ technology does a complete AC frequency analysis
of boards and IC packages. Supporting both pre- and post-layout studies, it quickly
pinpoints the best decap selections and placement locations to meet your
power-delivery network (PDN) needs at the lowest possible cost.
Sigrity OptimizePI technology is built on proven Cadence hybrid electromagnetic
circuit analysis technology in combination with the unique Sigrity optimization engine
to help you quickly pinpoint the best possible decap selections and placement locations.
Features
• Eliminates decap over-design for PCBs and IC packages
• Reduces PDN cost for new designs and post-production products
• Develops effective decap guidelines for packaged components
• Optimizes a PDN across the board/package interface
• Identifies both the number and locations for EMI decaps
• Robust and proven underlying hybrid EM/circuit analysis technology
• Intuitive and interactive visualization of PDN performance
• Simple to set up for pre- and post-layout decap optimization
• Visualize the power portion of your schematics with Cadence Allegro®
PowerTree™ data
• Capture setup information (models, net names, etc.) in a PowerTree GUI that
enables assignment of target impedence constraints
• Unique device impedance and EMI resonance checking
• Ability to support large designs that include both package and board data
• Optimized for flows with Cadence SiP Layout, Allegro Package Designer, and
Allegro PCB Designer
• Readily used in Mentor, Zuken, and Altium flows, accepting a mix of CAD
databases where needed for multi-structure design support
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