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HOME > Products > EDA tools > Digital Design and Signoff > Silicon Signoff

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	IP solutions

	Vendor：	Cadence Design Systems, Inc.
	Product Name：	QuickView Signoff Data Analysis Environment
	Product Introduce：

Provides production-proven, full-chip, high-performance chip-finishing system

Key Benefits

• Improves full-chip signoff productivity via seamless integration with Cadence
Physical Verification System, complete full-chip DRC/LVS/ERC review, job
submission, and error analysis within a single cockpit

• Fast loading, editing, and analysis of large layouts for GDSII and OASIS

• Easy-to-use, high-performance standalone chip-finishing system, with support
for LEF/DEF format for digital design review

Cadence® QuickView Signoff Data Analysis Environment is the industry’s production-proven full-chip
high-performance, high-capacity data-viewing, and standalone chip-finishing system that supports
multiple formats of design, layout, and manufacturing data.

The QuickView Signoff Data Analysis Environment is an easy-to-use, high-performance, and standalone
chip-finishing system that supports multiple formats of design, layout, and manufacturing data. The
QuickView Signoff Data Analysis Environment loads large layouts (GDSII, OASIS, LEF/DEF, and
manufacturing formats) in seconds, and provides a rich set of debugging features, including net
connectivity tracing, visualization, overlay, and GDSII/OASIS editing.

QuickView Signoff Data Analysis